--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   18:00:03 01/05/2010
-- Design Name:   
-- Module Name:   C:/Custom32Processor/MySOC/test_RegistersFile.vhd
-- Project Name:  MySOC
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: RegistersFile
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;


-- General package
use work.GeneralProperties.ALL;
 
ENTITY test_RegistersFile IS
END test_RegistersFile;
 
ARCHITECTURE behavior OF test_RegistersFile IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT RegistersFile
    PORT(         
           InputPort : in  STD_LOGIC_VECTOR ((bus_size - 1) downto 0);
           OutPortA : out  STD_LOGIC_VECTOR ((bus_size - 1) downto 0);
           OutPortB : out  STD_LOGIC_VECTOR ((bus_size - 1) downto 0);           
           WriteEnable : in  STD_LOGIC;
           WriteAddress : in  ProcessorRegisters;
			  ReadAddPortA : in  ProcessorRegisters;
           ReadAddPortB : in  ProcessorRegisters;
           ReadAEnable : in  STD_LOGIC;
           ReadBEnable : in  STD_LOGIC
        );
    END COMPONENT;
    

   --Inputs   
   signal InputPort : std_logic_vector((bus_size - 1) downto 0) := (others => '0');
   signal WriteEnable : std_logic := '0';
   signal WriteAddress : ProcessorRegisters := r0;
   signal ReadAddPortA : ProcessorRegisters := r0;
   signal ReadAddPortB : ProcessorRegisters := r0;
   signal ReadAEnable : std_logic := '0';
   signal ReadBEnable : std_logic := '0';

 	--Outputs
   signal OutPortA : std_logic_vector((bus_size - 1) downto 0);
   signal OutPortB : std_logic_vector((bus_size - 1) downto 0);
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: RegistersFile PORT MAP (          
          InputPort => InputPort,
          OutPortA => OutPortA,
          OutPortB => OutPortB,
          WriteEnable => WriteEnable,
          WriteAddress => WriteAddress,
          ReadAddPortA => ReadAddPortA,
          ReadAddPortB => ReadAddPortB,
          ReadAEnable => ReadAEnable,
          ReadBEnable => ReadBEnable
        );
 
   
   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
		WriteEnable <= '0';
      wait for 100 ns;	

      REPORT "Write Test ..." SEVERITY WARNING;
		WriteEnable <= '1';
		WriteAddress <= r0;
		InputPort <= conv_std_logic_vector(15, bus_size);
		wait for 100 ns;
		
		WriteEnable <= '0';
		wait for 100 ns;
		
		WriteEnable <= '1';
		WriteAddress <= r1;
		InputPort <= conv_std_logic_vector(14, bus_size);
		wait for 100 ns;
		
		WriteEnable <= '0';
		wait for 100 ns;
		
		WriteEnable <= '1';
		WriteAddress <= r2;
		InputPort <= conv_std_logic_vector(13, bus_size);
		wait for 100 ns;
		
		WriteEnable <= '0';
		wait for 100 ns;
		
		WriteEnable <= '1';
		WriteAddress <= r3;
		InputPort <= conv_std_logic_vector(12, bus_size);
		wait for 100 ns;
		
		WriteEnable <= '0';
		wait for 100 ns;
		
		WriteEnable <= '1';
		WriteAddress <= r4;
		InputPort <= conv_std_logic_vector(11, bus_size);
		wait for 100 ns;
		
		WriteEnable <= '0';
		wait for 100 ns;
		
		WriteEnable <= '1';
		WriteAddress <= r5;
		InputPort <= conv_std_logic_vector(10, bus_size);
		wait for 100 ns;
		
		WriteEnable <= '0';
		wait for 100 ns;
		
		WriteEnable <= '1';
		WriteAddress <= r6;
		InputPort <= conv_std_logic_vector(9, bus_size);
		wait for 100 ns;
		
		WriteEnable <= '0';
		wait for 100 ns;
		
		WriteEnable <= '1';
		WriteAddress <= r7;
		InputPort <= conv_std_logic_vector(8, bus_size);
		wait for 100 ns;
		
		WriteEnable <= '0';
		wait for 100 ns;
		
		WriteEnable <= '1';
		WriteAddress <= r8;
		InputPort <= conv_std_logic_vector(7, bus_size);
		wait for 100 ns;
		
		WriteEnable <= '0';
		wait for 100 ns;
		
		WriteEnable <= '1';
		WriteAddress <= r9;
		InputPort <= conv_std_logic_vector(6, bus_size);
		wait for 100 ns;
		
		WriteEnable <= '0';
		wait for 100 ns;
		
		WriteEnable <= '1';
		WriteAddress <= r10;
		InputPort <= conv_std_logic_vector(5, bus_size);
		wait for 100 ns;
		
		WriteEnable <= '0';
		wait for 100 ns;
		
		WriteEnable <= '1';
		WriteAddress <= r11;
		InputPort <= conv_std_logic_vector(4, bus_size);
		wait for 100 ns;
		
		WriteEnable <= '0';
		wait for 100 ns;
		
		WriteEnable <= '1';
		WriteAddress <= r12;
		InputPort <= conv_std_logic_vector(3, bus_size);
		wait for 100 ns;
		
		WriteEnable <= '0';
		wait for 100 ns;
		
		WriteEnable <= '1';
		WriteAddress <= r13;
		InputPort <= conv_std_logic_vector(2, bus_size);
		wait for 100 ns;
		
		WriteEnable <= '0';
		wait for 100 ns;
		
		WriteEnable <= '1';
		WriteAddress <= r14;
		InputPort <= conv_std_logic_vector(1, bus_size);
		wait for 100 ns;
		
		WriteEnable <= '0';
		wait for 100 ns;
		
		WriteEnable <= '1';
		WriteAddress <= r15;
		InputPort <= conv_std_logic_vector(0, bus_size);
		wait for 100 ns;
		
		WriteEnable <= '0';
		wait for 100 ns;

      REPORT "Read Test ..." SEVERITY WARNING;
		WriteEnable <= '0';
		ReadAEnable <= '1';
		ReadBEnable <= '1';
		ReadAddPortA <= r0;
		ReadAddPortB <= r0;		
		wait for 200 ns;
		
		WriteEnable <= '0';
		ReadAEnable <= '1';
		ReadBEnable <= '1';
		ReadAddPortA <= r1;
		ReadAddPortB <= r1;		
		wait for 200 ns;
		
		WriteEnable <= '0';
		ReadAEnable <= '1';
		ReadBEnable <= '1';
		ReadAddPortA <= r2;
		ReadAddPortB <= r2;		
		wait for 200 ns;
		
		WriteEnable <= '0';
		ReadAEnable <= '1';
		ReadBEnable <= '1';
		ReadAddPortA <= r3;
		ReadAddPortB <= r3;		
		wait for 200 ns;
		
		WriteEnable <= '0';
		ReadAEnable <= '1';
		ReadBEnable <= '1';
		ReadAddPortA <= r4;
		ReadAddPortB <= r4;		
		wait for 200 ns;
		
		WriteEnable <= '0';
		ReadAEnable <= '1';
		ReadBEnable <= '1';
		ReadAddPortA <= r5;
		ReadAddPortB <= r5;		
		wait for 200 ns;
		
		WriteEnable <= '0';
		ReadAEnable <= '1';
		ReadBEnable <= '1';
		ReadAddPortA <= r6;
		ReadAddPortB <= r6;		
		wait for 200 ns;
		
		WriteEnable <= '0';
		ReadAEnable <= '1';
		ReadBEnable <= '1';
		ReadAddPortA <= r7;
		ReadAddPortB <= r7;		
		wait for 200 ns;
		
		WriteEnable <= '0';
		ReadAEnable <= '1';
		ReadBEnable <= '1';
		ReadAddPortA <= r8;
		ReadAddPortB <= r8;		
		wait for 200 ns;
		
		WriteEnable <= '0';
		ReadAEnable <= '1';
		ReadBEnable <= '1';
		ReadAddPortA <= r9;
		ReadAddPortB <= r9;		
		wait for 200 ns;
		
		WriteEnable <= '0';
		ReadAEnable <= '1';
		ReadBEnable <= '1';
		ReadAddPortA <= r10;
		ReadAddPortB <= r10;		
		wait for 200 ns;
		
		WriteEnable <= '0';
		ReadAEnable <= '1';
		ReadBEnable <= '1';
		ReadAddPortA <= r11;
		ReadAddPortB <= r11;		
		wait for 200 ns;
		
		WriteEnable <= '0';
		ReadAEnable <= '1';
		ReadBEnable <= '1';
		ReadAddPortA <= r12;
		ReadAddPortB <= r12;		
		wait for 200 ns;
		
		WriteEnable <= '0';
		ReadAEnable <= '1';
		ReadBEnable <= '1';
		ReadAddPortA <= r13;
		ReadAddPortB <= r13;		
		wait for 200 ns;
		
		WriteEnable <= '0';
		ReadAEnable <= '1';
		ReadBEnable <= '1';
		ReadAddPortA <= r14;
		ReadAddPortB <= r14;		
		wait for 200 ns;
		
		WriteEnable <= '0';
		ReadAEnable <= '1';
		ReadBEnable <= '1';
		ReadAddPortA <= r15;
		ReadAddPortB <= r15;		
		wait for 200 ns;
		
		REPORT "Read different registers ..." SEVERITY WARNING;
		WriteEnable <= '0';
		ReadAEnable <= '1';
		ReadBEnable <= '1';
		ReadAddPortA <= r0;
		ReadAddPortB <= r15;		
		wait for 200 ns;
		
		REPORT "Read register r5(A,B) while writting on r6 255 ..." SEVERITY WARNING;
		WriteEnable <= '1';
		ReadAEnable <= '1';
		ReadBEnable <= '1';
		ReadAddPortA <= r5;
		ReadAddPortB <= r5;
	   WriteAddress <= r6;
		InputPort <= conv_std_logic_vector(255, bus_size);		
		wait for 200 ns;
		
		WriteEnable <= '0';
		wait for 100 ns;
		
		REPORT "Read register r6(A,B) while writting  on r6 100..." SEVERITY WARNING;
		WriteEnable <= '1';
		ReadAEnable <= '1';
		ReadBEnable <= '1';
		ReadAddPortA <= r6;
		ReadAddPortB <= r6;
	   WriteAddress <= r6;
		InputPort <= conv_std_logic_vector(88, bus_size);		
		wait for 200 ns;
		
		REPORT "Read register r5(A,B) ..." SEVERITY WARNING;
		WriteEnable <= '0';
		ReadAEnable <= '1';
		ReadBEnable <= '1';
		ReadAddPortA <= r5;
		ReadAddPortB <= r5;		
		wait for 200 ns;
		
		REPORT "Read register r6(A,B) (should be 88) ..." SEVERITY WARNING;
		WriteEnable <= '0';
		ReadAEnable <= '1';
		ReadBEnable <= '1';
		ReadAddPortA <= r6;
		ReadAddPortB <= r6;		
		wait for 200 ns;

      wait;
   end process;

END;
